1. Field of the Invention
This invention relates to semiconductor processing and, more particularly, a chemical-mechanical polishing apparatus and method for planarizing the upper surfaces of semiconductor substrates.
2. Description of the Relevant Art
Fabrication of integrated circuits upon semiconductor substrates (xe2x80x9cwafersxe2x80x9d) involves numerous processing steps. For example, the fabrication of a metal-oxide-semiconductor (MOS) integrated circuit includes the formation of trench isolation structures within a semiconductor substrate to separate each MOS field-effect transistor that will be made. The semiconductor substrate is typically doped with either n-type or p-type impurities. A gate dielectric, typically composed of silicon dioxide, is formed on the semiconductor substrate. For each MOSFET being made, a gate conductor is formed over the gate dielectric and a source and drain are formed by introducing dopant impurities into the semiconductor substrate. Conductive interconnect lines are then formed to connect the MOSFETs to each other and to the terminals of the completed integrated circuit. Modern high-density integrated circuits typically include multiple interconnect levels to provide all of the necessary connections. Multiple interconnect levels are stacked on top of each other with intervening dielectric levels providing electrical insulation between interconnect levels.
During integrated circuit fabrication, unwanted elevational disparities of the upper surface of the semiconductor substrate that can occur after certain processing steps may have a detrimental effect on subsequent processing steps. For example, prior to formation of interconnect levels of an integrated circuit, a dielectric is deposited upon the transistors that have been formed on the semiconductor substrate. As deposited, this dielectric typically will not have a planar upper surface but will instead tend to conform to the underlying topography. If these elevational disparities are not removed, subsequent processing steps may suffer from a variety of problems. For instance, an interconnect metal deposited upon the non-planar upper surface of the dielectric may exhibit step coverage problems. Step coverage is an indication of how well a film conforms to an underlying step. If the interconnect metal is not deposited with sufficient step coverage, interconnect lines patterned from the interconnect metal may suffer from open circuit failure. A non-planar surface may also cause depth-of-focus problems for subsequent lithographically-patterned layers. Depth-of-focus refers to the ability of a lithographic systems to focus radiation on a photoresist only over a limited thickness. If a portion of the photoresist is at a different elevation than the rest of the photoresist due to a non-planar underlying surface, the elevationally disparate portion of the photoresist may not be fully exposed by the lithographic system resulting in a patterning of the photoresist different from the desired pattern.
Chemical-mechanical polishing (CMP) is a prevalent technique for planarizing surfaces of semiconductor substrates and thereby avoiding the problems discussed above. CMP removes surface material and planarizes surfaces through chemical and mechanical abrasion of surface material. FIG. 1 illustrates a cross-sectional side view of a portion of a rotary CMP apparatus (xe2x80x9ctoolxe2x80x9d) while FIG. 2 illustrates a top view of the CMP tool. An example of a rotary CMP tool is the Auriga available from SpeedFam International, Inc. of Chandler, Ariz. Semiconductor wafer 10 is held in carrier 12 and is placed face down upon polishing pad stack 20. Although four carrier/wafer assemblies 14 are shown in FIG. 2, polishing pad stack 20 may have one to six carrier/wafer assemblies placed upon it depending on the size of wafer 10 relative to the size of polishing pad stack 20. Polishing pad stack 20 is affixed to platen 22. Both carrier 12 and platen 22 may rotate and their rotational speeds are independently adjustable. A polishing fluid, typically a slurry, is deposited on the surface of polishing pad stack 20 through conduit 24. The polishing slurry consists of an abrasive-particle-containing fluid that may be chemically reactive with one or more of the materials on the surface of the wafer. The polishing slurry occupies the interface between wafer 10 and polishing pad stack 20.
During the polishing process, carrier 12 and platen 22 are rotated at angular frequencies xcfx89c and xcfx89p, respectively, while carrier 12 applies a force F downward on wafer 10, typically referred to as xe2x80x9cdown forcexe2x80x9d. The polishing slurry chemically reacts with the surface material of wafer 10 while the movement of wafer 10 relative to polishing pad stack 20 causes the abrasive particles contained in the polishing slurry to strip the reacted material from wafer 10. The amount of material removed by CMP is governed by several variables including down force, carrier rotational speed, platen rotational speed, polishing time, and composition of the polishing fluid.
Polishing pad stack 20 includes polishing pad 16 and polishing pad 18 affixed to platen 22. Polishing pad 16 is preferably harder than polishing pad 18. Platen 22 provides rigid support for polishing pad stack 20. A typical pad stack used on CMP tools is an IC1000 stacked on top of a Suba IV. Both pads are manufactured by Rodel, Inc. of Phoenix, Ariz. Multiple pads are typically used to simultaneously improve both local flatness and global uniformity of the polished wafer. A problem with polishing pad stack 20 is that replacement of worn out pads is time consuming. Replacing pads requires that pads 16 and 18 be removed from platen 22 and then new pads must be affixed to platen 22. During the replacement process, the CMP tool is not available for use thereby increasing manufacturing costs.
FIG. 3 shows a portion of a wafer, which includes semiconductor substrate 30, in contact with polishing pad stack 20. Layer 32, which has surface irregularities that are to be removed, has been previously formed upon semiconductor substrate 30. Elevationally raised area 34 is in contact with hard polishing pad 16 which is attached to soft polishing pad 18. Polish pad 16 has deformed slightly and projects in toward elevationally depressed area 36. The harder polish pad 16 is, the less it will deform. The ideal CMP process would only remove material from elevationally raised area 34 and not from elevationally depressed area 36 and would result in surface 38 of layer 32 after polishing. Realistically, some material is removed from elevationally depressed area 36; however, material is removed at a higher rate from elevationally raised area 34 such that surface 40 results after polishing. Layer 32 has an average thickness t after polishing. In general, the flatness and location of actual polished surface 40 is desired to be as similar as possible to ideal polished surface 38.
It is also desired for surface 40 of the polished wafer to have good uniformity, which can be defined as average thickness t of layer 32 being the same at all locations on semiconductor substrate 30. Softer polishing pad 18 is placed underneath harder polishing pad 16 to improve uniformity of the polished wafer. Softer polishing pad 18 allows polishing pad stack 20 to partially conform to minor changes in the overall shape of the wafer. For instance, if semiconductor substrate 30 is slightly bowed, the polishing pad stack will also be slightly bowed so it can remain in contact with the wafer over its entire surface while the use of hard polishing pad 16 as the top polishing pad minimizes conformance of the polishing pad stack to local surface irregularities that are to be removed. In general, the CMP process parameters include a low down force, a high rotational speed, and a hard polishing pad to improve uniformity. Better uniformity generally results in increased yield, which is defined as the percentage of completed integrated circuits that are functional. Increased yield represents a reduction in the cost of manufacturing integrated circuits.
Linear CMP tools have been developed to improve the uniformity of polished wafers. FIG. 4 depicts a cross-sectional side view of a portion of a linear CMP tool. An example of a linear CMP tool is the Teres(trademark) manufactured by Lam Research Corporation of Fremont, Calif. Semiconductor wafer 50 is held in carrier 52 and placed face down upon belt 54. At most, two semiconductor wafers can be polished simultaneously by linear CMP tools. Belt 54 includes multiple polishing pads affixed to a thin metal backing. Typically, three polishing pads are required to cover the metal backing. Belt 54 is held in place and tensioned by rollers 56 and rotation of rollers 56 causes belt 54 to move. During the polishing process, a polishing fluid is applied to an upper surface of belt 54 through conduit 60. Carrier 52 rotates at an angular frequency xcfx89c while belt 54 passes underneath wafer 50 at speed xcexdb. Carrier 52 also applies a down force F on wafer 50. To prevent belt 54 from deflecting downward from this force, platen 58 is placed below belt 54 and located directly underneath wafer 50.
Platen 58 may be a solid fixture that provides rigid support of belt 54; however, for improved uniformity of the polished wafer, platen 58 may be a fluid-bearing platen. The fluid-bearing platen does not make contact with belt 54, but instead supports belt 54 to with a fluid flow. The pressure exerted by the fluid flow provides a counter force to down force F exerted by carrier 52. The flow rate at different locations on the fluid-bearing platen may be adjusted so that the wafer is polished at different rates at different locations so that improved uniformity results.
Problems may occur with the linear CMP due to its increased complexity. During polishing, belt 54 must be kept properly tensioned or the wafer being polished may be damaged or destroyed. Additionally, belt 54 has a tendency to wander off rollers 56 which may also damage or destroy the wafer being polished. The polishing pads are also subject to more stress since they must conform to the shape of rollers 56 as they pass over the rollers. Replacement of worn out pads is time consuming. After the old belt is removed, the new belt must be installed and properly tensioned and aligned so that it will function properly. During belt installation, the linear CMP tool is not available for use thereby increasing manufacturing costs.
Although a linear CMP tool with a fluid-bearing platen is often recognized as leaving polished wafers with better uniformity than most rotary CMP tools, the rotary CMP has higher throughput since it can polish multiple wafers simultaneously. Better uniformity of the polished wafers results in increased yield and reduced manufacturing costs; however, higher throughput increases productivity which also reduces manufacturing costs. Additionally, both types of CMP tools require multiple polishing pads. A rotary CMP tool typically uses two polishing pads stacked on top of each other while a linear CMP tool typically requires three polishing pads to cover the entire belt.
It therefore is desirable to develop an improved CMP tool that incorporates both good throughput and good uniformity while keeping the construction of the tool as simple as possible. It is also desirable to develop an improved CMP tool that requires only a single polishing pad that could be quickly replaced after it has worn out.
The problems described above are addressed in large part by a rotary CMP tool that employs multiple fluid-bearing platens. A single round polishing pad is affixed to a round pad backing that is a taut, thin metal membrane preferably composed of stainless steel. The polishing pad is preferably an industry-standard hard polishing pad. A holder is attached to the edges of the pad backing and facilitates rotation of the polishing pad and pad backing about their common center. A conduit allows a polishing fluid to be introduced onto an upper surface of the polishing pad. One or more wafers are held face down upon the upper surface of the polishing pad by carriers. The carriers apply a down force on the wafers. Each carrier and wafer pair rotates about its common center. Fluid-bearing platens are placed below a lower surface of the pad backing and located directly underneath each wafer. The fluid-bearing platens do not make mechanical contact with the pad backing. The fluid-bearing platens support the pad backing with a fluid flow. The pressure exerted by the fluid flow provides a counter force to the down force exerted by the carrier. Multiple zones of differing fluid flow rates within the fluid-bearing platen allow control of the polishing uniformity of the wafer. Additionally, the fluid flow rate distribution of each fluid-bearing platen can be individually adjusted. The fluid can be a liquid or gas and is preferably air.
The fluid-bearing platen can generate multiple zones of differing fluid flow rate by having a plurality of conduits within the platen. The flow rate of fluid through one conduit may be adjusted relative to the other conduits to produce differing flow rates. Preferably, the flow rate through each conduit can be individually adjusted to maximize the uniformity of the polished wafers. For example, if polished wafers are observed to have more material removed at the edges than at the center, the flow rate of conduits under the center of the wafer may be increased relative to the flow rate of conduits under the edge of the wafer and thereby improve the uniformity. Additionally, the distribution of flow rates for each fluid-bearing platen is adjustable independent of the other fluid-bearing platens so that the wafers polished over each platen exhibit good uniformity.
A rotary CMP tool with multiple fluid-bearing platens allows both good uniformity and high throughput. The ability to polish multiple wafers simultaneously provides a throughput equivalent to that of a standard rotary CMP tool. The use of fluid-bearing platens provides a uniformity of polished wafers equivalent to that of a linear CMP tool and therefore an improved yield of the completed integrated circuits over that of the standard CMP tool. Since the use of the rotary CMP tool with multiple fluid-bearing platens simultaneously allows good throughput and good yield, its use results in a significant reduction in manufacturing costs of integrated circuits.
The use of a single polishing pad also represents a simplification and a cost savings over the stack of two polishing pad typical of standard rotary CMP tools or the three pieces of polishing pad typically used by linear CMP tools. Pad replacement on the rotary CMP tool with multiple fluid-bearing platens is also simplified. Pad replacement can be accomplished by simply replacing the old pad and pad backing with a new pad and pad backing. The old pad may be removed and a new pad affixed to the old pad backing elsewhere. This results in an increase tool usage and therefore a decrease of manufacturing costs over the typical practice for a standard CMP tool of removing the old pad stack and affixing a new pad stack with the solid platen in situ.